CHAPTER IV

Realization of Star-Free Events


It has been shown by Krohn and Rhodes [9] and again by Zeiger [10], that any finite-state automaton can be constructed by a cascade of two-state reset machines and simple group accumulators (permutation machines). It has also been shown by Brzozowski [11] and Perles, Rabin and Shamir [15] that any definite event can be realized by a cascade of unit delays. Mayer [8] and Cohen and Brzozowski [14] have shown that every star-free regular event corresponds to a cascade of two-state reset machines, by invoking the Krohn-Rhodes theory as treated by A. Ginzburg [12], i.e. using a refinement of Zeiger's construction. The construction method presented here is closely related to Ginzburg's. One of the main differences is the use of the ross tree to produce a simpler construction.


4.1 Covers

Throughout this chapter we assume that the given event is in PF. The first step in the construction is to find a nested sequence of preserved covers (which Ginzburg calls "admissable decompositions" and Hartmanis and Stearns [13] call "set systems with S.P.") A cover Cn is any finite set of subsets Bi, called blocks, of S, the set of states of the automaton M, such that the union of all the Bi is the set S. Repeated blocks or blocks that are subsets of other blocks are permitted in a cover, but repeated states within a block are not permitted. A cover Cn is preserved if and only if each successor set of any of the blocks of Cn under any input sequence x in A* is contained in some block of Cn. A cover Cn+1 is finer than a cover Cn if and only if each block of Cn+1 is contained in some block of Cn, and at least one of those containments is proper. A nested sequence of preserved covers of an automaton is then a sequence of covers C0, C1, ..., Cp such that C0={(S)} and Cp={(s1), (s2), ..., (sn)} and each Cr+1 is finer than Cr, 0≤r<p. To find such a nested sequence we need some more definitions.

Note that there may be more than one dominant block in a cover.

In the following definition we consider loops in a tree. There are of course no loops in a tree, but when a branch terminates at a set equal to a previously encountered set, that branch is in effect an unfolded loop. This terminating set and those sets intervening between this appearance and the previous appearance of the set could be redrawn as a closed loop.

Note that in any cover there always exists at least one splittable set.

Now we can say that every cover has one and only one splitting set of blocks. Furthermore, we can divide the blocks of a cover into two types.

Note that no block of a set of resultant blocks is contained in any other block of that set, and the union of all the blocks of a set Di of resultant blocks is equal to its splitting block Bi. It is also obvious that the set of resultant blocks of any splitting block is unique.


4.2 The Cover Algorithm

To find the set of preserved covers, an algorithm is presented which obtains the required cover from the previous cover. The covers are presented in matrix form with the blocks of the cover appearing as entries in the matrix. The columns represent the entries of the previous matrix and are labelled by the coordinates of the respective entry in the previous cover matrix. The rows, for cover Cn, are labelled arbitrarily sn1, sn2, ..., snm.

To obtain the first cover matrix, assume the one row, one column trivial matrix with the single block of the trivial cover as the only entry.

{(S)}

The row and column need not be labelled in this case, as this represents the trivial cover C0 of one block of all the states and is only used to obtain C1, the first non-trivial cover by means of the general algorithm. The general algorithm, to obtain cover Cn from the previous cover Cn-1, follows below:

  1. For each block of the previous cover Cn-1, create a column of cover matrix Cn and label it with the coordinates of the respective block of Cn-1.
  2. Choose a splitting set of blocks C"n-1 in cover Cn-1.
  3. Fill each column belonging to a splitting block of Cn-1 with its set of resultant blocks, one resultant block per row, in such a way that corresponding resultant blocks appear in the same row of Cn. Note that there will be as many rows in this cover matrix as there are resultant blocks per splitting block.
  4. Place all the passive blocks of Cn-1 into their respective columns of Cn so that they all appear in the same row, which may be any of the rows already established in step (iii).
  5. Label the rows sn1, sn2, ... etc. The entries represent the blocks of the new cover Cn, and the remaining locations in the matrix are left blank.

This algorithm is used repeatedly until the trivial cover consisting of all the singletons is reached. At this point an example illustrates the algorithm.

Consider the automaton depicted by the state table in Figure 3.1.3a and construct the ross tree as shown in Figure 3.1.3b. We now start with the trivial cover C0. The process of finding the covers may be followed in Figure 4.2.1.

Figure 4.2.1
Finding the Covers

C0=   (ABCDEF)
C1= s12 (BCEF)
s11 (ADF)
C2= s22 (BEF)  
s21 (CEF) (ADF)
    s12 s12
C3= s32 (EF) (CEF) (DF)
s31 (BF)   (AF)
    s12s22 s12s21 s11s21
C4= s42     (CF)    
s41 (EF) (BF) (EF) (DF) (AF)
    s12s22s32 s12s22s31 s12s21s32 s11s21s32 s11s21s31
C5= s52 (F) (F) (F) (F) (F) (F)
s51 (E) (B) (C) (E) (D) (A)
    s12s22s32s41 s12s22s31s41 s12s21s32s42 s12s21s32s41 s11s21s32s41 s11s21s31s41

To obtain C1 we notice that the splitting set of blocks of C0 is the set of one splitting block {(ABCDEF)}. C1 must contain one column as C0 has one block. From the ross tree it is seen that the maximal observable subsets of (ABCDEF) are (BCEF) and (ADF). Thus they are the resultant blocks and are placed in two different rows arbitrarily labeled s11 and s12.

To find C2, (BCEF) is the only dominant block, and we have two columns, one for entry (BCEF) in C1 and one for (ADF). (BCEF) has two resultant blocks (BEF() and (CEF). (ADF), being passive, is just carried along and may be placed in either row of its own column. Notice the (BEF) (CEF) column has the coordinates of the (BCEF) entry of C1 and (ADF), of the (ADF) entry. Again the new rows are arbitrarily named s21 and s22.

To find C3, we have three dominant blocks. Two of them (ADF) and (BEF) are contained in a ross tree loop; hence {(ADF)(BEF)} is a splittable set. {(CEF)} alone is also a splittable set, but we will choose the former as our splitting set and consider the latter passive in this cover. We now have two sets of resultant blocks {(AF)(DF)} and {(BF)(EF)}. Notice that (AF) and (BF) must appear in the same row. (CEF) may be placed in either row. Again notice the labelling of the rows and columns.

To find C4 we split (CEF) and now (EF)(BF)(DF) and (AF) are considered passive and may be placed in any row as long as they are all in the same row.

To find C5 we have one large splittable and hence splitting set {(EF)(BF)(CF)(EF)(DF)(AF)} and, checking for corresponding resultant blocks, we obtain all the singletons as shown at the bottom of Figure 4.2.1.


4.3 Reset Machines

Before proceeding to the construction of the automaton it is necessary first to look at the building block. A generalized reset machine Mr, is an automaton with n states s1, s2, ..., sn and n+1 inputs i0, i1, i2, ..., in. Its transition function T, is shown in Figure 4.3.1a, where input i0 leaves the states as they are (that is, i0 is the identity input) and each of the inputs ij, j=1 to n, causes all the states to go to the single state sj.

Figure 4.3.1a
Reset Machine
  i0 i1 i2 . in
s1 s1 s1 s2 . sn
s2 s2 s1 s2 . sn
. . . . . .
sn sn s1 s2 . sn
Figure 4.3.1b
Ross Tree
Ross Tree

It may immediately be seen in Figure 4.3.1b that Mr is a permutation-free automaton. Any n-state reset machine, where n is greater than 2, may be decomposed into a number of two-state reset machines connected in parallel. In fact, the number of such machines is log 2n rounded up to the nearest integer. The procedure may be found in Hartmanis and Stearns [13], although for machines as simple as reset machines, this may be done by inspection. Two-state reset machines are of particular importance because they correspond to a common piece of circuitry, the set-reset flip-flop. In the hardware implementation two inputs called the set and the reset inputs appear as two separate physical inputs. This device corresponds to our two-state reset machine if we let one of our inputs i2 correspond to a signal on the physical set input, the other input i1 to the physical reset input and the identity input i0 to no signal on either physical input. Care must be taken not to allow signal to appear on both physical inputs at the same time, as this would be a fourth, undefined input for our two-state reset machine which would destroy the correspondence between this device and our model of a two-state reset machine. Set-reset flip-flops also have physical outputs corresponding to the set and reset states of the flip-flop. As these outputs indicate the state of the flip-flop we will label the outputs with the states they represent. For the purpose of the next section we will consider the more general n-state reset machines and assume a hardware device with n physical inputs and the same restrictions on multiple signals as the two-state device just considered.


4.4 The Interconnection Algorithm

We are now ready to consider the construction of the cascade of set-reset flip-flops that realize the permutation-free automaton M. With each cover matrix Cn of the automaton M, 1≤n≤p, we associate a reset machine Mrn with as many states as there are rows in the matrix. Each reset machine Mrn has as inputs, functions of the inputs to the automaton M and outputs of only the reset machines Mrm, where m<n. These input functions are arranged in such a manner that reset machine Mrn contributes information to the cascade, corresponding to the splitting of the blocks in cover Cn-1 to form resultant blocks in cover Cn. In this way, after the final reset machine Mrp, enough information has been contributed to distinguish between each individual state of the automaton M, since Cp consists of the set of all the singleton blocks.

To find the input functions of Mrn, we examine the types of transitions found in cover Cn-1 and see how these are carried over to cover Cn, as discussed in Lemma 4.2.1. The input functions are then arranged so that Mrn performs the appropriate splitting of blocks. We shall consider now the five possible transitions discussed in Lemma 4.2.1 and what is required of reset machine Mrn for each of them.

  1. Passive to passive. Since all the passive blocks of Cn-1 are in the same row of Cn, the required action in Mrn could be obtained by either an identity input or a reset input to that row; for simplicity, the identity is chosen.
  2. Splitting to passive. Since a splitting block in Cn-1 becomes a set of resultant blocks in Cn, (each resultant block in a different row) and since they must all go to one row in Cn, (the row used for the passive blocks) this transition in Mrn requires a reset to that row.
  3. Splitting onto splitting. Since each resultant block goes to one of its corresponding blocks under this type of transition, and corresponding blocks are in the same row, this transition requires an identity input for Mrn.
  4. Splitting to subset of splitting. As in transition type (ii) above, this transition is from many blocks in different rows to one block in one row. Hence this requires a reset input to that row in Mrn.
  5. Passive to subset of splitting. If the passive block and the subset of the splitting block appear in different rows of Cn, a reset input is required. If they appear in the same row then either a reset or an identity will do. For simplicity an identity will be used in this latter case. These two possibilities will be labeled type (v-a) and (v-b) respectively.

Since, in the definition of a cover, duplicate or contained blocks are allowed, care must be taken when they do occur. By looking at the previous cover it can immediately be seen which block is the true successor block of a column when that column initially appears to have more than one. That is if Bi appears to go to either Bjk or Bmp but in the previous cover Bi goes to Bm then we know that Bi goes only to Bmp in this cover.

Now a general algorithm can be given for the interconnections between the reset machines, using the ross tree.

  1. For each column in Cn locate the observable block of Cn-1 corresponding to it in the ross tree.
  2. For each successor of this block under a in A which is reached by a transition of type (ii), (iv) or (v-a), a factor consisting of the conjunction of all the terms labeling the column in Cn and the input a, is assigned to the input ink associated with the row k of Cn which includes that true successor.
  3. The input ink for each row k of Cn is the disjunction of all the factors assigned to it.

This algorithm is best demonstrated by an example:

Using the ross tree in Figure 3.1.3 and the covers C1 to C5 in Figure 4.2.1, the interconnections are obtained one machine at a time. The process may be followed in Figure 4.4.1, where portions of the ross tree have been included for convenience.

Figure 4.4.1
Finding the Interconnections
Interconnections

Consider first the cover C1 of one column. This column corresponds to the single block of C0 (ABCDEF). From the ross tree we see that under input 0 it goes to (ADF) via a transition of type (iv), hence contributing a factor of 0 to input i11. Similarly a 1 is contributed to i12. Since this is the only column in this cover we are finished and we have the following:

i11=0
i12=1

Consider next cover C2. The first column represents (BCEF) which from the ross tree can be seen to contribute s120 to i21 (type ii) and s121 to i22 (type v-a). Notice that (ADF) to (AF) is a transition of type (i) and hence does not contribute s110 to i21. Hence for this machine Mr2 the inputs are:

i21=s120+s121=s12
i22=s111

For cover C3 we have column (BEF) contributes s12s221 to i32 (type ii), but not s12s220 (type iii). Column (CEF) contributes nothing as s12s210 is type (v-b) and s12s211 is type (i). Notice in this last case that, in the ross tree, s12s211 yields (EF) which appears to be in either (EF) or (CEF) of C3. Looking at C2, we see that (CEF) under 1 goes to (CEF). Hence s12s211 goes to (CEF) which is a transition of type (i). In this case it does not matter as the other transition would have been of type (v-b), also a non-contributor. In general it is important to find the correct transition from the previous cover. Column (ADF) contributes s11s210 to i31 (type iv) but not s11s211 (type iii). Hence machine Mr3 has inputs:

i31=s11s210
i32=s12s221

For C4 we have (EF) going to (F) under 1 which could be anywhere. From C3 we see that (BEF) goes to (CF), hence (EF) goes to (F) in (CF) in C4, making this a type (v-a) transition which contributes s12s22s321 to i42 This case shows the importance of using the previous cover's transition to determine the true successor set. The second column (BF) contributes s12s22s311 to i42 (type v-a). The third column (CEF) contributes s12s21s320 to i41 (type ii) and s12s21s321 to i41 (type iv). Note that from C3 we can see that this last transition is type (iv) not (ii). The fourth column (DF) contributes nothing as both transitions are type (i). The last column also contributes nothing for the same reason. Hence machine Mr4 has inputs:

i41=s12s21s320+s12s21s321=s12s21s32
i42=s12s22s311=s12s22s321=s12s221

In cover C5 we have the two (EF) columns contributing s12s22s32s411 and s12s21s32s411 to i52 (type iv), all the other transitions are of type (iii). Hence the last machine Mr5 has only one input:

i52=s12s22s32s411+s12s21s32s411=s12s32s411

This completes the construction of a machine M to realize the event R=(I11(I00I)'11I)'. The machine consists of the five reset machines Mr1 to Mr5 interconnected as shown above and in Figure 4.4.2.

Figure 4.4.2
Interconnections
Interconnections

To prove the algorithm we borrow the following proofs from Mayer [8].


4.5 Hardware Implementation

To obtain the hardware configuration corresponding to the automaton constructed in the previous section, the physical inputs to each set-reset flip-flop must be driven by the appropriate disjunction of factors assigned by the interconnection algorithm. The disjunction may be realized by a logical OR gate. Each of the factors is a conjunction of the coordinates of the entries of the previous cover, that is, a conjunction of the appropriate states of the previous flip-flops and the original inputs. The conjunction may be realized by a logical AND gate. The state of the previous flip-flops may be obtained from their physical outputs. Note that the circuit considered is a clocked synchronous circuit. Again this hardware implementation is best shown by an example. Using the automaton constructed in the example of the previous section, we obtain the physical implementation shown in Figure 4.5.1.

Figure 4.5.1
Hardware Implementation
Hardware Implementation

Notice that the interconnection algorithm, by its nature, ensures that signal will not appear on more than one of the physical inputs to any one flip-flop, hence ensuring the validity of our model.

Figure 4.5.2a
Three-State Reset Machine
Three-State Reset Machine
Figure 4.5.2b
Three-State Reset Machine
Three State Reset Machine

In Figures 4.5.2a and 4.5.2b we show how a three-state set-reset flip-flop may be constructed from two two-state flip-flops by a simple partitioning of states. Returning to the implementation of Figure 4.5.1, it is a simple matter to write the state table for it, as shown in Figure 4.5.3.

Figure 4.5.3
State Table of Realization
state 0 1
00000 00000 11000
00001 00001 11001
00010 00010 11010
00011 00011 11011
00100 00000 11100
00101 00001 11101
00110 00010 11110
00111 00011 11111
01000 01000 11000
01001 01001 11001
01010 01010 11010
01011 01011 11011
01100 01100 11100
01101 01101 11101
01110 01110 11110
01111 01111 11111
10000 00000 10000
10001 00001 10001
10010 00010 10010
10011 00011 10011
10100 00100 10101
10101 00101 10101
10110 00100 10100
10111 00101 10101
11000 00000 10110
11001 00001 10111
11010 00010 10110
11011 00011 10111
11100 00100 10111
11101 00101 10111
11110 00110 10110
11111 00111 10111

Comparing this state table with the original one in Figure 3.1.3 we see immediately that if we let state A correspond to the state (00000), we may quickly obtain the other correspondences. They are listed here:

A - (00000)
B - (11000)
C - (10110)
D - (00100)
E - (10100) and (11100)
F - (10101), (10111), (00101), (11101), (00001), (11001)

We have so far neglected the output of the automaton. In the automaton of Figure 3.1.3, to realize the event

(I11(I00I)'11I)',

the set (A) of final states defines the output required. In the feedback-free cascade of set-reset flip-flop realization shown in Figure 4.5.1 the output is obtained by the conjunction of the states that correspond to the original state A, that is s11s21s31s41s51. This output may be realized by an AND gate having those five inputs.


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